rv32i-mla
verilog, accelerator
RV32I based 3 cycle pipelined CPU and accelerator experiments on PYNQ-Z2, written in Verilog. Focused on simple processor design, memory-mapped interfaces, and hardware/software integration.
Selected Work
hardware-security
verilog · hardare-security
FPGA-based hardware security experiments, Weak PUF readout from SRAM, AES-128 bit implementation, CPA and DFA on AES, mostly written in Verilog.
fpga-programming
synthesis · bring-up
KIT FPGA Programming Praktikum (lab) WS25/26 exercises, all solved on Verilog, synthesis flow, board bring-up, and hardware debugging.
Notes
Elsewhere
- hello@alpblkba.dev
- PGP/GPG
- 0x5805EA560CCCAF6C
- github
- github.com/alpblkba
- linkedin.com/in/alpblkba
- location
- Karlsruhe, Germany